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ISL59833
Data Sheet March 5, 2007 FN6334.1
200MHz Single Supply Video Driver With Charge Pump
The ISL59833 is a revolutionary device that allows true singlesupply operation of video amplifiers. Designed for systems requiring output swing below ground but lacking a negative power supply, the ISL59833 generates the required negative rail internally from a +3.3V power supply. This allows for DC-accurate coupling of video onto a 75 double-terminated line. The buffers have an integrated 6dB, eliminating the need for external gain-setting resistors. An external reference voltage can be applied to the REF pin to shift the analog video level down by the desired amount.
Features
* Triple single-supply buffer * Generates negative rail from from single +3.3V supply * No output DC blocking capacitor needed * 200MHz -3dB bandwidth * 50MHz 0.1dB bandwidth * Fixed gain of 2 output buffer * Amplifier enable/disable function control * Outputs are high impedance in power-down mode * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER PART TAPE & (Note) MARKING REEL ISL59833IAZ 59833 IAZ 7" PACKAGE (Pb-free) PKG. DWG. #
Applications
* Driving video
16 Ld QSOP MDP0040 16 Ld QSOP MDP0040
ISL59833IAZ-T7 59833 IAZ
Pinout
ISL59833 (16 LD QSOP) TOP VIEW
RIN 1 GIN 2 BIN 3 REF 4 VEE 5 GND 6 VEEOUT 7 DGND 8 16 ROUT 15 GOUT 14 BOUT 13 VCC 12 EN 11 VCC 10 NC 9 DVCC
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59833
Absolute Maximum Ratings
VCC, Supply Voltage between VS and GND . . . . . . . . . . . . . . . . .5V VIN, VREF . . . . . . . . . . . . . . . . . . . . . . . . . .VCC + 0.3V, VEE - 0.3V Voltage between VIN and VREF . . . . . . . . . . . . . . . . . . . . . . . . . .2V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Thermal Information
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
AC Electrical Specifications
PARAMETER BW - 3dB 3dB Bandwidth
VCC = DVCC = +3.3V, REF = GND, TA = +25C, RL = 150, unless otherwise specified. CONDITIONS VOUT = 200mVPP VOUT = 2VPP MIN TYP 200 100 50 500 0.07 0.06 6MHz 6MHz -90 -70 20 168 IEE = 0mA to 10mA 9 30 With Bead Core to DVCC 10 30 MAX UNIT MHz MHz MHz V/s % dB dB nV/Hz MHz mV mV mV
DESCRIPTION
BW 0.1dB SR dG dP XT I VN fCP Load Reg VRIPPLE
0.1dB Bandwidth Slew Rate Differential Gain Differential Phase Hostile Crosstalk Input to Output Isolation Input Noise Voltage Charge Pump Switching Frequency VEE Load Regulation Output Amp Ripple Voltage
VOUT = 2VPP VIN = 2VPP
DC Electrical Specifications
PARAMETER V+ VG% G IIN VOS VOUT +
VCC = DVCC = +3.3V, REF = GND, TA = +25C, RL = 150, unless otherwise specified. CONDITIONS MIN 3.0 RL = 150, VOUT = -1V to +2.5V RL = 150 VIN = 0V to 1.5V VREF = 0 RL = 75 RL = 150 -25 2.4 2.7 0.5 0.1 7 2.5 2.9 -1.3 -1.5 50 80 -40 500 1 50 2.3 62 3.5 -18 -1 -1.2 1 +25 TYP MAX 3.6 1.5 UNIT V % % A mV V V V V mA mA k A dB
DESCRIPTION Supply Range Gain Error Gain Matching Analog Input Leakage Current Output Offset Voltage Maximum Output Voltage
VOUT -
Minimum Output Voltage
RL = 75 RL = 150
IOUT + IOUT ZOUT IREF PSRR
Output Current Output Current Disabled Output Impedance Reference Input Leakage Current Power Supply Rejection Ratio
RL = 10, VIN = 1.2V RL = 10, VIN = -0.3V EN = 3.3V (Amp Disabled)
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FN6334.1 March 5, 2007
ISL59833
DC Electrical Specifications
PARAMETER IS Supply Current VCC = DVCC = +3.3V, REF = GND, TA = +25C, RL = 150, unless otherwise specified. (Continued) CONDITIONS EN = GND (Amp Enabled) EN = 3.3V (Amp Disabled) MIN TYP 97 60 MAX 130 90 UNIT mA mA
DESCRIPTION
Pin Descriptions
PIN NUMBER 1 PIN NAME RIN PIN FUNCTION Analog input EQUIVALENT CIRCUIT
VCC
VEE CIRCUIT 1
2 3 4
GIN BIN REF
Analog input Analog input Reference input High impedance input controlling offset of amplifiers
Reference Circuit 1 Reference Circuit 1
VCC RIN GIN BIN x1 3 ROUT GOUT BOUT
+ -
REF
VEE CIRCUIT 2
5
VEE
Chip substrate (negative power supply for amplifiers)
VCC
VEE OUT -+ DVCC CHARGE PUMP DGND CIRCUIT 3 VEE
6 7 8 9 10 11, 13
GND VEE OUT DGND DVCC NC VCC
Analog ground Charge pump output Charge pump ground Charge pump supply voltage Not connected Positive power supply Reference Circuit 3 Reference Circuit 3 Reference Circuit 3
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FN6334.1 March 5, 2007
ISL59833 Pin Descriptions (Continued)
PIN NUMBER 12 PIN NAME EN PIN FUNCTION Power-down Input Low: Normal Operation High: Power-down Charge Pump and Amplifiers EQUIVALENT CIRCUIT
VCC
VEE CIRCUIT 4
14
BOUT
Analog output
VCC
VEE CIRCUIT 5
15 16
GOUT ROUT
Analog output Analog output
Reference Circuit 5 Reference Circuit 5
Typical Performance Curves
3 2 1 0 500 -1 -2 -3 1M 150 75 10M 100M 1G -5 100k 1M 10M FREQUENCY (Hz) 100M 1G AV = +2 CL = 0pF NORMALIZED GAIN (dB) 3 5 AV = +2 RL = 500 9pF 4.7pF 2.2pF 1 0pF
NORMALIZED GAIN (dB)
1k
-1
-3
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD
5 NORMALIZED OUTPUT (dB) 0 -5 -10 -15 -20 -25 -30 -35 1 100 200 300 400 500 FREQUENCY (MHz) AV = +2 CL = 0pF RL = 500
300 AV = +2 RL = 500 GAIN ROLL-OFF (MHz) 240 -3dB ROLL-OFF
180
120
60 -0.1dB ROLL-OFF 0 2.25 2.80 3.35 3.90 4.45 5.00
TOTAL SUPPLY VOLTAGE, VCC - VEE (V)
FIGURE 3. VREF PIN OUTPUT FREQUENCY RESPONSE
FIGURE 4. GAIN ROLL-OFF
FN6334.1 March 5, 2007
4
ISL59833 Typical Performance Curves (Continued)
1.6 AV = +2 RL = 500 CL = 3.9pF CROSS TALK (dB) 1.2 PEAKING (dB) -30 AV = +2 -40 RL = 500 -50 -60 -70 -80 -90 -100 -110 0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 -120 100k 1M 10M FREQUENCY (Hz) 100M 1G DISABLED ENABLED
0.8
0.4
SUPPLY VOLTAGE (V)
FIGURE 5. PEAKING vs SUPPLY VOLTAGE
FIGURE 6. CROSS TALK CHANNEL TO CHANNEL (TYPICAL)
-20 AV = +2 -30 RL = 500 -40 ISOLATION (dB) -50 -60 -70 -80 -90 -100 100k 1M 10M FREQUENCY (Hz) 100M 1G SUPPLY CURRENT (mA)
120 100 80 60 40 20 0 1.0 AV = +2 RL = 500
1.5
2.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
200 -3dB BANDWIDTH (MHz) AV = +2 RL = 500 SUPPLY CURRENT (mA) 160
95 AV = +2 RL = 500 VCL = 3.3V 90
120
85
80
40 -0.1dB 0 25 55 85 TEMPERATURE (C) 115 145
80
75 25
55
85 TEMPERATURE (C)
115
145
FIGURE 9. BANDWIDTH vs TEMPERATURE
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
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FN6334.1 March 5, 2007
ISL59833 Typical Performance Curves (Continued)
100 VCC = DVCC = 3.3V -10 VAC = 100mVP-P RL = 150 -20 PSRR (dB) 100k 1M FREQUENCY (Hz) 10M 100M -30 -40 -50 -60 -70 0.01 10k -80 10k 100k 1M 10M 0
10 IMPEDANCE ()
1
0.1
FREQUENCY (Hz)
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 12. POWER SUPPLY REJECTION RATIO vs FREQUENCY
1k HARMONIC DISTORTION (dBc) VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz)
-30 -40 -50 -60 -70 -80 -90 -100 100 1k 10k 100k 1M 10M 0 10 20 30 40 FREQUENCY (Hz) FUNDAMENTAL FREQUENCY (MHz) 3RD HD 2ND HD THD
100
10
eN
1
IN+ IN-
0.1 10
FIGURE 13. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs FREQUENCY
-30 -40 -50 THD (dBc) -60 -70 -80 -90 0.5 THD FIN = 1MHz 1.0 1.5 2.0 2.5 3.0 3.5 IRE OUTPUT VOLTAGE (VP-P) THD FIN = 10MHz DIFFERENTIAL GAIN (%) 0
-0.02
-0.04
-0.06
-0.08
FIGURE 15. THD vs OUTPUT VOLTAGE
FIGURE 16. DIFFERENTIAL GAIN
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FN6334.1 March 5, 2007
ISL59833 Typical Performance Curves (Continued)
0 VOLTS (500mV/DIV) DIFFERENTIAL PHASE ()
-0.02
-0.04
-0.06
-0.08 IRE TIME (2s/DIV)
FIGURE 17. DIFFERENTIAL PHASE
FIGURE 18. DISABLE TIME
VOLTS (500mV/DIV)
TIME (200ns/DIV)
VOLTS (50mV/DIV)
TIME (10ns/DIV)
FIGURE 19. ENABLE TIME
FIGURE 20. SMALL SIGNAL RISE AND FALL TIMES
0 -10 VOLTS (500mV/DIV) -20 NOISE (dBV) -30 -40 -50 -60 -70 -80 -90 TIME (10ns/DIV) 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (Hz)
FIGURE 21. LARGE SIGNAL RISE AND FALL TIMES
FIGURE 22. NOISE FLOOR WITH CHARGE PUMP HARMONICS
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FN6334.1 March 5, 2007
ISL59833 Typical Performance Curves (Continued)
3.25 BACKDRIVE CURRENT (mA) 1.6 BACKDRIVE ACROSS 5 RESISTOR TYPICAL CHANNEL 1.2 VCC = 3.3V 0.8
OUTPUT RANGE (V)
3.00
2.75
0.4
2.50 50
AV = +2 CL = 3.9pF 250 450 650 850 1050
0 0 1 2 3 4 5 BACKDRIVE VOLTAGE (V)
LOAD RESISTANCE ()
FIGURE 23. MAXIMUM OUTPUT MAGNITUDE vs LOAD RESISTANCE
FIGURE 24. BACKDRIVE VOLTAGE vs CURRENT AMP DISABLED OUTPUT LOADING
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1.0 791mW 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
QS OP J 16 A= +1 58 C /W
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 1.116W
J QS OP 16 12 C /W
A= +1
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6334.1 March 5, 2007
ISL59833 Block Diagram
VCC
RIN
+ 6dB ROUT
REF GIN + 6dB GOUT
BIN
+ 6dB DVCC CHARGE PUMP VEE VOUT = 2VIN - VREFERENCE BOUT
VEE-OUT
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FN6334.1 March 5, 2007
ISL59833 + DC-Restore Solution
1 IN1 2 COM1 3 NC1
IN2 16 COM2 15 NC2 14 V+ 13 NC 12 NC3 11 COM3 10 IN3 9 R9 2k R10 2k 1 RIN ROUT 16 GOUT 15 BOUT 14 VCC 13 EN 12 VCC 11 NC 10 DVCC 9 C15 R4 R5 R6 75 75 75 VCC C1 0.1F C14 20pF C13 20pF Pb
10
YO R1 75 Pb R2 75 C4 C5 C6 Pr R3 75 VCC
FN6334.1 March 5, 2007
R7 2k
4 V5 GND 6 NC4 7 COM4 8 IN4
(No Connect)
ISL43140
CN = Option for lower charge pump noise
C12 20pF YO
0.1F 0.1F 2 GIN 0.1F 3 BIN C7 0.1F 4 REF VEE (-1.6V) 1k R12 5 VEE 6 GND OFFSET CONTROL C11 0.1F 7 VEEOUT 8 DGND
ISL59833
Pr
ENABLE 2 1 0.1F 3
VCC VCC GND + C16 1F
VCC
ISL59833 1 COMP C4 0.1F 2 COMP
SYNC OUT VIDEO IN VDD 8 OUT 7 RESET 6 BACK PORCH 5 OUT
C8 0.1F
Option: Panasonic 120 Bead EXC3BP121H Lower Amp output noise from charge pump
3 VSYNC OUT C10 0.1F 4 GND
R13 C9 0.1F 681k
EL1881
ISL59833 Demo Board Schematic
RED_IN R1 75 RED_OUT GREEN_IN R2 75 1 RIN 2 GIN 3 BIN C4 0.1F 4 REF 5 VEE 6 GND C2 0.1F 7 VEEOUT 8 DGND ROUT 16 GOUT 15 BOUT 14 VCC 13 EN 12 VCC 11 NC 10 DVCC 9 C5 0.1F R4 R5 R6 75 75 GREEN_OUT 75 VCC C3 0.1F
BLUE_OUT
R3 75
ENABLE 2 1 3
VCC
VCC
R4
R8
499 1k OFFSET CONTROL
Option: Panasonic 120 Bead EXC3BP121H Lower Amp output noise from charge pump
Description of Operation and Application Information
Theory Of Operation
The ISL59833 is a highly practical and robust marriage of three high bandwidth, high speed, low power, rail-to-rail voltage feedback amplifiers with a charge pump to provide a negative rail without an additional power supply. Designed to operate with a single supply voltage range from 0V to 3.3V, the ISL59833 eliminates the need for a split supply with the incorporation of a charge pump capable of generating a bottom rail as much as 1.6V below ground for a 4.9V range on a single 3.3V supply. This performance is ideal for NTSC video with its negative-going sync pulses. THE AMPLIFIER The ISL59833 fabricated on a di-electrically isolated high speed 5V Bi-CMOS process with 4GHz PNPs and NPN transistor exceeding 20GHz - perfect for low distortion, low power demand and high frequency circuits. While the ISL59833 utilizes somewhat standard voltage mode feedback topologies, there are many non-standard analog features providing its outstanding bandwidth, rail-to-rail operation, and output drive capabilities. The input signal initially passes through a folded cascode, a topology providing enhanced frequency response by essentially fixing the base collector voltage at the junction of the input and gain stage. The collector of each input device looks directly into an emitter that is tied closely to ground through a resistor and biased with a very stable DC source. Since the voltage of this collector is "locked stable" the effective bandwidth limiting of the Miller capacitance is greatly reduced. The signal is then passed through a second fully-
realized differential gain stage and finally through a proprietary common emitter output stage for improved rail-to-rail output performance. The result is a highly-stable, low distortion, low power, and high frequency amplifier capable of driving moderately capacitive loads with near rail-to-rail performance. INPUT OUTPUT RANGE The three amplifier channels have an input common mode voltage range from 0.15V below the bottom rail to within 100mV of the positive supply, VS+ pin (Note: bottom rail is established by the charge pump at negative one half the positive supply). As the input signal moves outside the specified range, the output signal will exhibit increasingly higher levels of harmonic distortion. And of course, as load resistance becomes lower, the current drive capability of the device will be challenged and its ability to drive close to each rail is reduced. For instance, with a load resistance of 1k the output swing is within a 100mV of the rails, while a load resistance of 150 limits the output swing to within around 300mV of the rails. AMPLIFIER OUTPUT IMPEDANCE To achieve near rail-to-rail performance, the output stage of the ISL59833 uses transistors in the common emitter configuration, typically producing higher output impedance than the standard emitter follower output stage. The exceptionally high open loop gain of the ISL59833 and local feedback reduces output impedance to less than a 2 at low frequency. However, since output impedance of the device is exponentially modulated by the magnitude of the open loop gain, output impedance increases with frequency as the open loop gain decreases with frequency. This inductive-like effect of the output impedance is countered in the ISL59833
FN6334.1 March 5, 2007
11
ISL59833
with proprietary output stage topology, keeping the output impedance low over a wide frequency range and making it possible to easily and effectively drive relatively heavy capacitive loads (see Figure 11). THE CHARGE PUMP The ISL59833 charge pump provides a bottom rail up to 1.65V below ground while operating on a 0V to 3.3V power supply. The charge pump is internally regulated to one-half the potential of the positive supply. This internal multi-phase charge pump is driven by a 110MHz differential ring oscillator driving a series of inverters and charge storage circuitry. Each series inverter charges and places parallel adjoining charge circuitry slightly out of phase with the immediately preceding block. This generates a negative rail of about -1.6V with a low amplitude ripple voltage from the charge pump action. Some of this ripple is coupled into the output signals at a very low amplitude, as seen in Figure 22. The ripple on the outputs is typically well below the noise floor of the signal. There are two ways to further reduce the output supply noise: * Add a 120 bead in series between VCC and DVCC. This reduces the coupling between the charge pump and the analog amplifier supplies. * Add a 20pF capacitor between the back load 75 resistor and ground (see "ISL59833 + DC-Restore Solution" on page 10). This will attenuate frequencies above 100MHz. The system operates at sufficiently high frequencies that any related charge pump noise is far beyond standard video bandwidth requirements. Still, appropriate bypassing discipline must be observed, and all pins related to either the power supply or the charge pump must be properly bypassed. See "Power Supply Bypassing and Printed Circuit Board Layout" on page 14.
IN+
INOUT
BIAS
FIGURE 27. SIMPLIFIED SCHEMATIC
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FN6334.1 March 5, 2007
ISL59833
THE VREF PIN Applying a voltage to the VREF pin simply places that voltage on what would usually be the ground side of the gain resistor of the amplifier, resulting in a DC-level shift of the output signal. Applying 100mV to the VREF pin would apply a -100mV DC level shift to the outgoing signal. The charge pump provides sufficient bottom room to accommodate the shifted signal. VREF may be connected to ground for back porch at ground. The ISL59833 buffers the VREF voltage before applying it to the triple amplifiers, isolating the input from the amplifiers and allowing it to be driven by moderate-impedance voltage sources. THE VEE PIN The VEE pin is the output pin for the charge pump. A voltmeter applied to this pin will display the output of the charge pump. This pin does not affect the functionality of the part. One may use this pin as an additional voltage source. Keep in mind that the output of this pin is generated by the internal charge pump and a fully regulated supply that must be properly bypassed. We recommend a 0.1F ceramic capacitor placed as close to the pin and connected to the ground plane of the board. INPUT, OUTPUT AND SUPPLY VOLTAGE RANGE The ISL59833 is designed to operate with a single supply voltage range of from 0V to 3.3V. The need for a split supply has been eliminated with the incorporation of a charge pump capable of generating a bottom rail as much as 1.6V below ground, for a 4.9V range on a single 3.3V supply. This performance is ideal for NTSC video with its negative-going sync pulses. VIDEO PERFORMANCE For good video performance, an amplifier is required to maintain the same output impedance and the same frequency and phase response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150 because of the change in output current with changing DC levels. Special circuitry has been incorporated into the ISL59833 for the reduction of output impedance variation with the current output. This results in outstanding differential gain and differential phase specifications of 0.06% and 0.1, while driving 150 at a gain of +2. Driving higher impedance loads would result in similar or better differential gain and differential phase performance. NTSC The ISL59833 (generating a negative rail internally) is ideally suited for NTSC video with its accompanying negative-going sync signals, which is easily handled by the ISL59833 without the need for an additional supply as the ISL59833 generates a negative rail with an internal charge pump referenced at negative 1/2 the positive supply. YPbPr YPbPr signals originating from a DVD player requiring three channels of very tightly-controlled amplifier gain accuracy present no difficulty for the ISL59833. Specifically, this standard encodes sync on the Y channel and it is a negativegoing signal, which is easily handled by the ISL59833 without the need for an additional supply as the ISL59833 generates a negative rail placed at negative 1/2 the positive supply. Additionally, the Pb and Pr are bipolar analog signals and the video signals are negative-going, and again, easily handled by the ISL59833. DRIVING CAPACITIVE LOADS AND CABLES The ISL59833 (internally-compensated to drive 75 cables) will drive 10pF loads in parallel with 1k with less than 5dB of peaking. If less peaking is required, a small series resistor, usually between 5 to 50, can be placed in series with the output. This will reduce peaking at the expense of a slight closed loop gain reduction. When used as a cable driver, double termination is always recommended for reflectionfree performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. The ISL59833 is a triple amplifier designed to drive three channels; simply deal with each channel separately as described in this section. DC-RESTORE When the ISL59833 is AC-coupled it becomes necessary to restore the DC reference for the signal. This is accomplished with a DC-restore system applied between the capacitive "AC" coupling and the input of the device. Refer to "ISL59833 + DC-Restore Solution" on page 10. AMPLIFIER DISABLE The ISL59833 can be disabled and its output placed in a high impedance state. The turn-off time is around 25ns and the turn-on time is around 200ns. When disabled, the amplifier's supply current is reduced to 80mA typically, reducing power consumption. The amplifier's power-down can be controlled by standard TTL or CMOS signal levels at the EN pin. The applied logic signal is relative to the GND pin. Letting the EN pin float or applying a signal that is less than 0.8V above GND will enable the amplifier. The amplifier will be disabled when the signal at EN pin is 2V above GND. The VEE charge pump remains active. OUTPUT DRIVE CAPABILITY The ISL59833 does not have internal short-circuit protection circuitry. A short-circuit current of 80mA sourcing and 150mA sinking for the output is connected half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output
FN6334.1 March 5, 2007
13
ISL59833
current never exceeds 40mA, after which the electromigration limit of the process will be exceeded and the part will be damaged. This limit is set by the design of the internal metal interconnections. POWER DISSIPATION With the high output drive capability of the ISL59837, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current i = Number of output channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat.
Power Supply Bypassing and Printed Circuit Board Layout
Strip line design techniques are recommended for the input and output signal traces. As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split-internal supplies are to be used. In this case, the VSpin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is also very important.
(EQ. 1)
Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing:
V OUT i PD MAX = V S x I SMAX + ( V S - V OUT i ) x ----------------RL i
(EQ. 2)
for sinking:
PD MAX = V S x I SMAX + ( V OUT i - V S ) x I LOAD i (EQ. 3)
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FN6334.1 March 5, 2007
ISL59833 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6334.1 March 5, 2007

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